Radio Frequency Design of Fast Locking Digital Phase Locked Loop

Phase locked loop (PLL) is a control system that generates a signal that has a fixed relation to the phase of a reference signal. The performance of PLL is primarily dependent on the lock time, it is the time the PLL takes to adapt and settle after a sudden change of the input signal frequency. It is desired to design a novel fast locking digital PLL. The high speed high throughput applications needed for information technology demand that the lock time should be as small as possible. The fast locking digital PLL proposed is consisting of two main stages, namely fine stage and coarse stage. The fine stage is having a phase detector, a multiple charge ump and voltage control oscillator while the coarse stage mainly consists the fast locking algorithm. It is having a frequency comparator array, a 3:8 decoder and an encoder. The PLL designed is having a centre frequency 500MHz with 20% deviation. The efforts are made to reduce the lock time and to achieve a high degree of accuracy in the work. A comparison for the locking time and the capture ranges is made between two technologies i.e. 0.18 μm and 50nm. It is found that there is great reduction in the locking time when 50nm technology is used. The locking time is found around 60 to 70nsec. The comparison is also made between the locking times of respective conventional and fast locking digital phase locked loop. The simulations are done using Advance Design System (ADS) software.