Review on Comparator Design for High Speed ADCs

Modern ultra-deep-sub micron (UDSM) technologies introduce several new challenges in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits feedback circuits linearity. Another issue in analog design is the drop in supply voltages. Till date comparators are analyzed with their DC, AC and Transient analysis. High speed, low-offset voltage and less resolution are essential factors for high-speed applications like Analog-to-Digital Converters (ADCs) used in RF front end. High speed comparator influences the overall performance of ADCs directly. The selection of particular topology is dependent upon the requirements and application as well as the performance required for that application. The advanced comparators are now used in integrated circuits because they are successful in removing many of limitations. Still, further advancement in comparator is necessary as downscaling of technology is increasing. This paper is about the survey on CMOS comparators. Different comparator topologies are mentioned with their key features. The comparative analysis table shows the specifications of different topologies.