• DocumentCode
    3114692
  • Title

    A wide-range programmable high-speed CMOS frequency divider

  • Author

    Larsson, Patrik

  • Author_Institution
    IFM, Linkoping Univ., Sweden
  • Volume
    1
  • fYear
    1995
  • fDate
    30 Apr-3 May 1995
  • Firstpage
    195
  • Abstract
    We present a fully programmable frequency divider for high-speed CMOS applications. High degree of pipelining makes the maximum clock rate independent of the number of bits in the divider. A maximum operating frequency of 400 MHz has been measured on dividers implemented in a 1 μm CMOS process
  • Keywords
    CMOS logic circuits; counting circuits; frequency dividers; 1 micron; 400 MHz; high-speed CMOS applications; maximum clock rate; maximum operating frequency; pipelining; programmable frequency divider; BiCMOS integrated circuits; Clocks; Counting circuits; Delay; Frequency conversion; Logic; Pipeline processing; Signal generators; Switches; Switching circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
  • Conference_Location
    Seattle, WA
  • Print_ISBN
    0-7803-2570-2
  • Type

    conf

  • DOI
    10.1109/ISCAS.1995.521484
  • Filename
    521484
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3114692