Delay Performance and Implementation of Quaternary Logic Circuits

Application of multiple-valued logic (MVL) in the design of digital devices opens additional opportunities. Multiple-valued logic also offers a possibility of increasing the functional complexity, implementing circuits that can perform comparable to the binary circuits. The main objective of this work is to design quaternary logic cells and with quaternary inputs and quaternary outputs. Logic Cells are designed based on voltage mode circuits and implemented using CMOS technology and compare its performance with binary ones.