The use of hierarchical information to test large controllers

Author

Fummi, F. ; Sciuto, D.

Author_Institution

Dipt. di Elettronica, Politecnico di Milano, Italy

fYear

1997

fDate

28-31 Jan 1997

Firstpage

325

Lastpage

328

Abstract

Gate-level test pattern generators require insertion of scan paths to handle the flat gate-level representation of a large sequential controller. In contrast, we present a testing methodology based on the hierarchical finite state machine model. Such a model is used to specify very complex control devices by means of a top-down design approach. Our approach allows the generation of compact test sets with very high stuck-at fault coverages, without any DfT logic

Keywords

control system CAD; controllers; finite state machines; hardware description languages; logic CAD; logic gates; logic testing; sequential circuits; DfT logic; complex control devices; gate-level representation; gate-level test pattern generators; hardware description language; hierarchical finite state machine model; hierarchical information; large controller testing; large sequential controller; scan paths; stuck-at fault coverage; testing methodology; top-down design approach; Automata; Circuit faults; Circuit testing; Fault diagnosis; Hardware design languages; Logic devices; Logic testing; Sequential analysis; Test pattern generators; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific

Conference_Location

Chiba

Print_ISBN

0-7803-3662-3

Type

conf

DOI

10.1109/ASPDAC.1997.600172

Filename

600172