Title :
Multiple fault detection in logic resources of FPGAs
Author :
Huang, Wei Kang ; Meyer, Fred J. ; Lombardi, Fabrizio
Author_Institution :
Dept. of Electron. Eng., Fudan Univ., Shanghai, China
Abstract :
An approach is proposed to detect multiple faults in FPGAs. The approach exploits the testability of the AND tree and OR tree with the configurability and programmability of SRAM-based FPGAs. The proposed AND tree- and OR tree-based testing structure is simple and the conditions for constant testability can easily be satisfied. Test generation for only a single CLB is required as the AND/OR approach scales to larger FPGAs. CLB test generation can assume any desired fault model. Any number of faulty CLBs in the chip can be detected
Keywords :
fault diagnosis; field programmable gate arrays; logic testing; AND tree; CLB test generation; OR tree; SRAM-based FPGA; configurability; fault model; logic resources; multiple fault detection; programmability; testability; Computer science; Consumer electronics; Costs; Fault detection; Field programmable gate arrays; Programmable logic arrays; Routing; Sequential analysis; Testing; Wires;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1997. Proceedings., 1997 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
0-8186-8168-3
DOI :
10.1109/DFTVS.1997.628324
