A novel power gated digitally controlled oscillator

Author

Lotfy, Amr M. ; Ghoneima, Maged ; Abdel-moneum, Mohamed

Author_Institution

Nanoelectron. Integrated Syst. Center (NISC), Nile Univ., Giza, Egypt

fYear

2011

fDate

Nov. 30 2011-Dec. 2 2011

Firstpage

1

Lastpage

4

Abstract

In this paper a novel power gated digitally controlled oscillator (DCO) is presented. The DCO is suitable for integration in various systems such as clock generation circuits, clock and data recovery, and clocking schemes for high speed links. Simulations of the proposed DCO on 65nm TSMC technology show frequency range of 2.5 GHz to 6.8 GHz across all corners. The proposed DCO consumes only 1.7 mW at 3 GHz and 3.2 mW at 6.8 GHz with estimated layout area of 70*70 μm². The phase noise of the free running DCO is -92 dBc/Hz measured at 1 MHz offset from a 3.4 GHz center frequency.

Keywords

clock and data recovery circuits; oscillators; phase noise; DCO; clock generation circuit; clock-and-data recovery; frequency 1 MHz; frequency 2.5 GHz to 6.8 GHz; frequency 3 GHz; frequency 3.4 GHz; high speed link; phase noise; power 1.7 mW; power 3.2 mW; power gated digitally controlled oscillator; size 65 nm; Clocks; Jitter; Logic gates; Phase locked loops; Phase noise; Sensitivity; All Digital PLLs; Digitally Controlled Oscillator;

fLanguage

English

Publisher

ieee

Conference_Titel

Energy Aware Computing (ICEAC), 2011 International Conference on

Conference_Location

Istanbul

Print_ISBN

978-1-4673-0466-5

Electronic_ISBN

978-1-4673-0464-1

Type

conf

DOI

10.1109/ICEAC.2011.6136677

Filename

6136677