A design-for-testability expert system for silicon compilers

Author

van Riessen, R.P. ; Kerkhoff, H.G. ; Janssen, J.M.J.

Author_Institution

MESA Res. Inst., Twente Univ., Enschede, Netherlands

fYear

1991

fDate

15-17 April 1991

Firstpage

10

Lastpage

15

Abstract

This paper describes a design-for-testability expert system for the selection of the most appropriate test method for every macro within an IC. The interface with the system designer is user-friendly and together with an efficient search mechanism this expert system can be used as a framework for all types of macros. This tool will be used in a self-test compiler, which generates the layout of self-testable macros automatically. The self-test compiler can be part of a silicon compilation system and thus contribute to the integration of testability into the design process.<>

Keywords

VLSI; circuit layout CAD; expert systems; integrated circuit testing; design process; design-for-testability expert system; layout; macro; most appropriate test method; search mechanism; self-test compiler; silicon compilers; Automatic testing; Built-in self-test; Circuit testing; Design for testability; Expert systems; Integrated circuit testing; Knowledge based systems; Process design; Silicon compiler; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers

Conference_Location

Atlantic City, NJ, USA

Type

conf

DOI

10.1109/VTEST.1991.208125

Filename

208125