Use of CrossCheck test technology in practical applications

Author

Chandra, Susheel ; Gheewala, Tushar ; Sucar, Hector ; Swan, George

Author_Institution

CrossCheck Technol. Inc., San Jose, CA, USA

fYear

1991

fDate

15-17 April 1991

Firstpage

16

Lastpage

21

Abstract

The CrossCheck technique is beginning to gain acceptance as an effective low-cost solution to the ASIC testability problem. The technique provides massive observability by embedding test circuitry into the ASIC device. This allows highly accurate defect modeling and simulation with less computational resources than conventional techniques. This paper describes CrossCheck test technology and present results on its application to real-life designs. All these designs are sequential in nature with multiple, gated and asynchronous clocks. Bridging, comprehensive (opens and shorts) as well as conventional stuck-at I/O fault coverage, and CPU time and memory requirements are presented.<>

Keywords

application specific integrated circuits; built-in self test; integrated circuit testing; logic testing; ASIC testability problem; CPU time; CrossCheck test technology; asynchronous clocks; computational resources; defect modeling; gated clocks; memory requirements; multiple clocks; observability; stuck-at I/O fault coverage; test circuitry; Application specific integrated circuits; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Costs; Integrated circuit testing; Logic; Observability; Probes;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers

Conference_Location

Atlantic City, NJ, USA

Type

conf

DOI

10.1109/VTEST.1991.208126

Filename

208126