DocumentCode
3116154
Title
Power-down integrated circuit built-in self-test structures
Author
Levy, Paul S.
Author_Institution
VLSI Technol. Inc., Tempe, AZ, USA
fYear
1991
fDate
15-17 April 1991
Firstpage
30
Lastpage
33
Abstract
Built-in self-test structures composed of logic elements are isolated from the host circuitry by means of separate Test VDD, so that it appears as an open circuit during normal operation of the IC. The separate Test VDD is employed to re-configure the host circuit and operate the test circuitry in the test mode. When Test VDD is removed, the test circuit powers down and disconnects from the host becoming invisible to the normal operation of the IC.<>
Keywords
built-in self test; integrated circuit testing; logic arrays; logic testing; IC testing; built-in self-test structures; host circuitry; logic elements; open circuit; power-down operation; test circuitry; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Costs; Design engineering; Integrated circuit testing; Logic devices; Logic testing; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location
Atlantic City, NJ, USA
Type
conf
DOI
10.1109/VTEST.1991.208128
Filename
208128
Link To Document