Statistical and transient channel modeling for crosstalk, bit error, jitter, and EMI

This paper describes a SerialATA 3.0 Gb/s channel created using one-, two-, and three-dimensional models. These various models have been combined with circuit simulation techniques to provide channel bit error rates (BER) under different de-emphasis settings. Analysis of the channel was performed using an aggressor-victim-aggressor simulation strategy that included Gaussian random jitter (RJ) and deterministic jitter in the form of duty cycle distortion (DCD). Finally, upon completion of the statistical solutions, various bit patterns and edge rates are chosen to act as the excitation source for near- and far-field plots on a backplane board. This technique provides an innovative simulation strategy that combines full channel analysis including radiated emissions dependent on drive strength and bit patterns.