• DocumentCode
    3116288
  • Title

    The advantages of boundary-scan testing

  • Author

    Dingle, Stephen L. ; Lacroix, Luke D. ; Twombly, Peter A.

  • Author_Institution
    IBM Gen. Technol. Div., Essex Junction, VT, USA
  • fYear
    1991
  • fDate
    15-17 April 1991
  • Firstpage
    71
  • Lastpage
    77
  • Abstract
    Boundary scan has been used extensively by IBM in custom logic, standard cell, and gate array logic chips. Actual implementations of boundary-scan methods used in testing these chips are discussed. The benefits of this approach are reviewed, and an economic analysis of the cost savings attributable to boundary scan are presented.<>
  • Keywords
    application specific integrated circuits; cellular arrays; logic arrays; logic testing; IBM; boundary-scan testing; cost savings; custom logic; economic analysis; gate array logic; standard cell; Circuit testing; Costs; Latches; Logic arrays; Logic devices; Logic testing; Pins; Software tools; System testing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
  • Conference_Location
    Atlantic City, NJ, USA
  • Type

    conf

  • DOI
    10.1109/VTEST.1991.208136
  • Filename
    208136
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3116288