• DocumentCode
    3116371
  • Title

    Issues of integrating the IEEE Std 1149.1 into a gate array

  • Author

    Cortez, Robert ; Dandapani, Ramaswami ; Yeager, Mike

  • Author_Institution
    United Technol. Microelectron. Center, Colorado Springs, CO, USA
  • fYear
    1991
  • fDate
    15-17 April 1991
  • Firstpage
    92
  • Lastpage
    97
  • Abstract
    Use of boundary-scan to test systems at the production and field levels has taken on a greater importance due to the development of surface mount technology. The IEEE Standard 1149.1 offers a documented approach to the implementation of boundary-scan. United Technologies Microelectronics Center (UTMC) integrated the standard into an ASIC gate array; this paper presents that implementation and addresses issues arising from the integration not covered specifically in the standard.<>
  • Keywords
    application specific integrated circuits; logic arrays; logic testing; surface mount technology; ASIC gate array; IEEE Standard 1149.1; United Technologies Microelectronics Center; boundary-scan; gate array; surface mount technology; Circuit testing; Driver circuits; Integrated circuit testing; Logic arrays; Logic testing; Microelectronics; Production systems; Springs; Surface-mount technology; System testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
  • Conference_Location
    Atlantic City, NJ, USA
  • Type

    conf

  • DOI
    10.1109/VTEST.1991.208139
  • Filename
    208139
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3116371