Title :
Issues of integrating the IEEE Std 1149.1 into a gate array
Author :
Cortez, Robert ; Dandapani, Ramaswami ; Yeager, Mike
Author_Institution :
United Technol. Microelectron. Center, Colorado Springs, CO, USA
Abstract :
Use of boundary-scan to test systems at the production and field levels has taken on a greater importance due to the development of surface mount technology. The IEEE Standard 1149.1 offers a documented approach to the implementation of boundary-scan. United Technologies Microelectronics Center (UTMC) integrated the standard into an ASIC gate array; this paper presents that implementation and addresses issues arising from the integration not covered specifically in the standard.<>
Keywords :
application specific integrated circuits; logic arrays; logic testing; surface mount technology; ASIC gate array; IEEE Standard 1149.1; United Technologies Microelectronics Center; boundary-scan; gate array; surface mount technology; Circuit testing; Driver circuits; Integrated circuit testing; Logic arrays; Logic testing; Microelectronics; Production systems; Springs; Surface-mount technology; System testing;
Conference_Titel :
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location :
Atlantic City, NJ, USA
DOI :
10.1109/VTEST.1991.208139
