DocumentCode
3116485
Title
A multilayered ceramic (MLC) interface design for 125+MHz performance wafer probing (of SRAMs)
Author
Belansek, George ; Loomis, Peter ; Towler, Fred ; Warner, Charles ; Wheeler, Donald
Author_Institution
IBM Gen. Technol. Div., Essex Junction, VT, USA
fYear
1991
fDate
15-17 April 1991
Firstpage
118
Lastpage
122
Abstract
A design is presented using a multilayered ceramic (MLC) substrate as the basis for the wafer-tester interface. A 27*27 matrix of pads on 225 mu m centers is contacted; this design replaces a hand-wire interface between the wafer probe and tester performance board. Significant reductions in signal crosstalk and power supply noise are realized.<>
Keywords
SRAM chips; integrated circuit testing; probes; multilayered ceramic; pad matrix; power supply noise; signal crosstalk; wafer probe; wafer probing; wafer-tester interface; Assembly; Ceramics; Crosstalk; Inductance; Power supplies; Probes; Random access memory; Testing; Voltage; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location
Atlantic City, NJ, USA
Type
conf
DOI
10.1109/VTEST.1991.208145
Filename
208145
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