Title :
Circuit-level classification and testability analysis for CMOS faults
Author :
Midkiff, Scott F. ; Bollinger, S. Wayne
Author_Institution :
Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Abstract :
The authors examine tests for short and open faults in CMOS circuits considering both IDDQ and logic observation test methods. Short and open faults are classified according to a topological classification that considers the type of fault, fault location, and affected transistor structure. The testability of each fault classification is considered for both optimistic and pessimistic assumptions. Circuit-level simulation is used to illustrate the classification.<>
Keywords :
CMOS integrated circuits; failure analysis; fault location; integrated circuit testing; CMOS faults; IDDQ testing; circuit level classification; fault location; logic observation test methods; open faults; short faults; testability analysis; topological classification; CMOS logic circuits; Circuit faults; Circuit simulation; Circuit testing; Conducting materials; Fault detection; Integrated circuit modeling; Integrated circuit testing; Logic testing; Semiconductor device modeling;
Conference_Titel :
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location :
Atlantic City, NJ, USA
DOI :
10.1109/VTEST.1991.208157
