Design of an asynchronous digital system with B-ternary logic

Some of the recent digital systems have a serious clock skew problem which comes from huge hardware implementations and high speed operations in VLSI´s. To overcome this problem, clock distribution techniques and more notably, asynchronous system design methodologies, have been investigated. Since, the latest asynchronous digital systems use two-rail logic with two-phase data transfer manner, more than two-fold hardware is required in comparison with the synchronous system. In this article, we present design of asynchronous digital system which is based on B-ternary logic so as to process binary data. The system consists of data-path and its controller. We provide B-ternary two-phase binary data processing in the data-path and its control procedure, which is based on shake-hand protocol. The functional units of the system are presented, that is, ternary-in binary-out memory with request/acknowledge detector and control unit. These units are fabricated with ternary NOR, NAND, INVERTER gates and ternary Muller´s C-elements