DocumentCode
3117077
Title
Session 6: Signal processing and processor designs
Author
Chillet, Daniel
Author_Institution
IRISA, University of Rennes, France
fYear
2011
fDate
2-4 Nov. 2011
Firstpage
1
Lastpage
1
Abstract
This session presents several experiences in the processor design domain for signal processing. The signal processing algorithms must generally support real hard real time constraints, and in this context the execution resources need to be very efficient. Designing specific processors or specific dedicated architectures is then a good issue to ensure the performances. Several specific architectures are presented in the following papers, and the authors present the result obtained and compare them with other solutions.
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Architectures for Signal and Image Processing (DASIP), 2011 Conference on
Conference_Location
Tampere, Finland
Print_ISBN
978-1-4577-0620-2
Electronic_ISBN
978-1-4577-0619-6
Type
conf
DOI
10.1109/DASIP.2011.6136865
Filename
6136865
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