• DocumentCode
    3117292
  • Title

    Hardware/software co-design of dataflow programs for reconfigurable hardware and multi-core platforms

  • Author

    Roquier, Ghislain ; Bezati, Endri ; Thavot, Richard ; Mattavelli, Marco

  • Author_Institution
    Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland
  • fYear
    2011
  • fDate
    2-4 Nov. 2011
  • Firstpage
    1
  • Lastpage
    7
  • Abstract
    The possibility of specifying both software and hardware components from a unified high-level description of an application is a very attractive design approach. However, despite the efforts spent for implementing such an approach using general purpose programming languages, it has not yet shown to be viable and efficient for complex designs. One of the reasons is that the sequential programming model does not naturally provide explicit and scalable parallelism and composability properties that effectively permits to build portable applications that can be efficiently mapped on different kind of heterogeneous platforms. Conversely dataflow programming is an approach that naturally provides explicit parallel programs with composability properties. This paper presents a methodology for the hardware/software co-design that enables, by direct synthesis of both hardware descriptions (HDL), software components (C/C++) and mutual interfaces, to generate an implementation of the application from an unique dataflow program, running onto heterogeneous architectures composed by reconfigurable hardware and multi-core processors. Experimental results based on the implementation of a JPEG codec onto an heterogeneous platform are also provided to show the capabilities and flexibility of the implementation approach.
  • Keywords
    hardware description languages; hardware-software codesign; programming languages; C/C++; HDL; JPEG codec; dataflow programming; dataflow programs; hardware components; hardware descriptions; hardware/software co-design; multi-core platforms; multi-core processors; programming languages; reconfigurable hardware; sequential programming model; software components; Field programmable gate arrays; Hardware; Hardware design languages; Multicore processing; Programming; Software; dataflow programming; hardware/software co-design; multi-core processor; reconfigurable hardware;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design and Architectures for Signal and Image Processing (DASIP), 2011 Conference on
  • Conference_Location
    Tampere
  • Print_ISBN
    978-1-4577-0620-2
  • Electronic_ISBN
    978-1-4577-0619-6
  • Type

    conf

  • DOI
    10.1109/DASIP.2011.6136875
  • Filename
    6136875