Power consumption improvement with residue code for fault tolerance on SRAM FPGA

The reliability of new SRAM FPGA (Field Programmable Gate Array) devices, which are the first components launched for each new generation of transistor, is difficult to estimate. Their increasing use on electronic boards in both terrestrial and space applications necessitates the development of fault tolerant techniques in the wake of growing soft error rates (SER). In this article, In this article, a concurrent error detection and correction scheme using residue codes is proposed and designed. The results express the gain for power consumption and circuit area compared for other solutions for fault detection or fault correction.