A VLSI implementation of a cellular rotator array

A description is given of the design of a systolic VLSI chip for the implementation of signal-processing algorithms that may be decomposed into simple real rotations. Applications of this chip include projection operators and discrete Fourier and cosine transforms. Large problems may be computed by tilting together many chips for increased throughput. A CMOS VLSI chip containing 138000 transistors in a 5×3 array of rotators has been designed, fabricated, and tested. The chip has a 32-MHz clock and performs real rotations at a rate of 30 MHz. The systolic nature of the chip makes use of fully synchronous bit-serial interconnects and a very regular structure. The result is a very simple and quickly implemented hardware solution