DocumentCode
3118469
Title
High-level synthesis for security and trust
Author
Rajendran, Jeyavijayan ; Huan Zhang ; Sinanoglu, Ozgur ; Karri, Ramesh
Author_Institution
Polytech. Inst. of New York Univ., New York, NY, USA
fYear
2013
fDate
8-10 July 2013
Firstpage
232
Lastpage
233
Abstract
Trustworthiness of System-on-Chips (SoCs) is undermined by malicious logic (trojans) in third party intellectual properties (3PIPs). Concurrent Error Detection (CED) techniques can be adapted to detect malicious outputs generated by trojans. Further, by using a diverse set of 3PIP vendors and operation-to-3PIP-to-vendor allocation constraints, one can prevent collusions between 3PIPs from the same vendor. These security constraints to detect malicious outputs and to prevent collusion have been incorporated into the allocation step of high-level synthesis.
Keywords
high level synthesis; industrial property; security of data; system-on-chip; trusted computing; 3PIP; CED; concurrent error detection techniques; high-level synthesis; malicious logic; malicious outputs; operation-to-3PIP-to-vendor allocation constraints; security constraints; system-on-chips; third party intellectual properties; trojans; trustworthiness; Benchmark testing; Hardware; Resource management; System-on-chip; Transient analysis; Trojan horses;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium (IOLTS), 2013 IEEE 19th International
Conference_Location
Chania
Type
conf
DOI
10.1109/IOLTS.2013.6604087
Filename
6604087
Link To Document