DocumentCode
3118550
Title
Bit map control processor (BMCP) design
Author
Sumi, Masahiko ; Kai, Naoyuki ; Tanaka, Shigeru ; Minagawa, Tsutomu ; Nagashima, Ichiro ; Hamai, Tsuneo ; Mori, Junji
Author_Institution
Toshiba Corp., Kawasaki, Japan
fYear
1988
fDate
16-19 May 1988
Abstract
A graphic processor, featuring 320-Mb/s bit BLT (bit boundary block transfer) speed, was developed using a novel memory cycle scheme. The key to the system design is a C/Unix-based RTL simulator program, which replaced breadboard hardware. The authors describe the BMCP architecture, the design step, and the design methodology
Keywords
C language; circuit CAD; computer architecture; computer graphic equipment; digital simulation; microprocessor chips; 320 Mbits/s; C/Unix; CMOS; LSI; RTL simulator program; architecture; bit boundary block transfer; bit map control processor; computer graphics; design; graphic processor; memory cycle scheme; microprocessor chips; Cathode ray tubes; Computer architecture; Computer graphics; Displays; Hardware; Magnetooptic recording; Microcomputers; Process control; Process design; Trademarks;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location
Rochester, NY
Type
conf
DOI
10.1109/CICC.1988.20826
Filename
20826
Link To Document