Jitter attenuation phase locked loop using switched capacitor controlled crystal oscillator

A jitter attenuation, narrow-bandwidth phase-locked loop (PLL) consisting of a switched-capacitor controlled crystal oscillator (SCCXO) and a countdown sequential-logic phase/frequency detector (PFD) is described. By varying the loading capacitance dynamically, the SCCXO frequency is adjusted according to the duty cycle of the control signal. The experiment results show that a PLL of less than 2-Hz loop bandwidth and input jitter rejection up to 30 unit intervals is achieved in 3000 square mils of silicon area using 3- μm CMOS technology. The intrinsic jitter output is 0.03 UI