A PLL based clock and data recovery circuit with high input jitter tolerance

A clock and data recovery circuit for a TI network is described. A fully integrated phase-locked loop (PLL) is used to extract the carrier signal embedded in the data stream. Two trimming DACs (digital-to-analog converters) simultaneously bring the voltage-controlled-oscillator (VCO) center frequency and the PLL closed-loop bandwidth to their specified values. A triple sampler captures the jittering data and aligns them with the recovered clock. The input jitter tolerance of this circuit is at least three times higher than that of the previously reported PLL-based clock and data recovery circuit