Title :
A 10.7-MHz switched-capacitor bandpass filter
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Abstract :
The author discusses basic design issues such as Q reduction, noise enhancement, op-amp settling, and power consumption associated with MHz-range switched-capacitor bandpass filters. Experimental results are presented for a sixth-order, all-pole, differential CMOS bandpass filter which has a center frequency of 10.7 MHz and a Q of 25 with a 42-MHz clock rate. Fabricated with a 2.25-μm gate, double-poly CMOS technology, the prototype filter occupies 2 mm2 and dissipates approximately 500 mW. As a result of imperfect settling, the measured center frequency of the filter exhibits a typical exponential error as the sampling rate is increased. A relation between the minimum bias current of the input stage and the center frequency is compared to the theoretical minimum
Keywords :
CMOS integrated circuits; band-pass filters; switched capacitor filters; 10.7 MHz; 2.25 micron; 42 MHz; 500 mW; IC; Q reduction; differential CMOS bandpass filter; double-poly CMOS technology; exponential error; measured center frequency; noise enhancement; operational amplifier settling; power consumption; switched-capacitor bandpass filter; Active filters; Band pass filters; Clocks; Energy consumption; Frequency; Low pass filters; MOS capacitors; Operational amplifiers; Resonator filters; Sampling methods;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20851
