The effect of contact placement on drive currents in 1.25 μm gate arrays: measured and simulated

In the design of CMOS standard-cell and gate-array devices as well as full-custom designs, it is common practice to use a minimum number of source and drain contacts to provide as much routing flexibility as possible for maximum packing density or space utilization. Often devices can be contacted with only a single contact to the source and/or drain regions. This can lead to a serious degradation in device performance due to an increase in the effective source/drain series resistance. This results in part from a spreading resistance effect, leading to current crowding near the contacts because of the potential drop along the width of the device in the source/drain regions. The authors quantitatively study this degradation using device measurements and the two-dimensional device simulator PISCES-IIB for its impact on device designs in a 1.25 μm CMOS gate-array process