Variation status in 100nm CMOS process and below

This paper addresses a new variability diagnostics and variability design methodology in the sub-100nm process era. We developed a 130nm-DMA(Device Matrix Array) test structure which diagnoses within-die device and circuit variations. And then we enhanced it for 90nm process. Our experiments show a significant increase of MOS Vth and Ids variation in 90nm process. It is found that the Vth variation is caused by Line-Edge Roughness(LER) effects as well as dopant-fluctuation under the active gate area. Foundry-provided worst-comer SPICE models were also intensively evaluated. Because of lack of detail investigation on within-die variation data at the foundry, it is found that the model parameters may suffer from unrealistic variation guard-band in both device performances and circuit characterizations. It reveals the worst-comer of the foundry practically covers only 1.5-sigma for small size MOSFETs used in Library cells, which is clarified by the measured wafer data with the DMA test structure.