Test structures and analysis techniques for estimation of the impact of layout on MOSFET performance and variability

Author

Saxena, Sharad ; Minehane, Seán ; Cheng, Jianjun ; Sengupta, Manidip ; Hess, Christopher ; Quarantelli, Michele ; Kramer, Glenn M. ; Redford, Mark

Author_Institution

PDF Solutions, Richardson, TX, USA

fYear

2004

fDate

22-25 March 2004

Firstpage

263

Lastpage

266

Abstract

The performance and variability of transistors with nanometer-scale feature sizes is sensitive to their layout style and environment. This paper describes the use of an enhanced MOS array test structure to provide accurate and precise estimates of the impact of layout on transistor characteristics for an advanced 130nm CMOS technology. Enhanced MOS arrays, combined with statistical analysis of the measurements, provide reliable information on the impact of layout on the transistor characteristics. This can then form the basis for technology development, design rule development and modeling.

Keywords

MOSFET; design of experiments; nanoelectronics; semiconductor device measurement; semiconductor device testing; 130 nm; MOSFET performance; MOSFET variability; advanced CMOS technology; design rule development; enhanced array test structure; layout style; nanometer-scale feature sizes; test structures; CMOS technology; Lithography; MOSFET circuits; Manufacturing; Performance analysis; Semiconductor device modeling; Shape; Statistical analysis; Testing; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2004. Proceedings. ICMTS '04. The International Conference on

Print_ISBN

0-7803-8262-5

Type

conf

DOI

10.1109/ICMTS.2004.1309492

Filename

1309492