Test circuits for extracting sub-100nm MOSFET technology variations with the MOSFET model HiSIM

We propose an efficient, test-circuit-based method to extract not only CMOS-device parameter variations but also to simultaneously separate intra-chip from inter-chip variations. The method is demonstrated by using a cascode-current-source and a differential-amplifier-stage with feed-back-coupling as the test-circuits and the drift-diffusion MOSFET model HiSIM for the circuit simulation. The result shows that the proposed test circuits, when constructed only with n-MOSFETs or p-MOSFETs, enables to separate inter- and intra-chip technology variations in a direct way.