DocumentCode :
3120221
Title :
Performance analysis of Montgomery multiplier for public key cryptosystem
Author :
Kakde, Sandeep ; Somulu, G. ; Zode, Pradnya
Author_Institution :
Dept. of Electron. Eng., Yashwantrao Chavan Coll. of Eng., Nagpur, India
fYear :
2013
fDate :
4-6 July 2013
Firstpage :
1
Lastpage :
5
Abstract :
Modular multiplication finds the major role in RSA Cryptography and Elliptical Curve Cryptography. Timing analysis measures the delay along the various timing paths and verifies the performance and operation of the design. We have implemented a 256-bit Modular multiplier using Montgomery Reduction Algorithm in VHDL. The output of the Montgomery multiplier is Z=X*Y R-1 mod M. Both RSA key generation component and data encryption component are too big to fit into a single Altera Cyclone II Device on Field Programmable platform, so that we are unable to test them in real hardware. However, each sub-component was simulated in Model-Sim SE 6.0 and Altera Quartus II 8.0 and proved functionally correct.
Keywords :
hardware description languages; multiplying circuits; public key cryptography; Altera Cyclone II device; Altera Quartus II 8.0; Model-Sim SE 6.0; Montgomery multiplier; Montgomery reduction algorithm; RSA cryptography; RSA key generation component; VHDL; data encryption component; delay measurement; elliptical curve cryptography; field programmable platform; modular multiplication; modular multiplier; performance analysis; public key cryptosystem; timing analysis; timing paths; word length 256 bit; Adders; Algorithm design and analysis; Cryptography; Delays; Hardware; Software; Software algorithms; Carry Save Adder; Cryptography; Modular Arithmetic; Montgomery Algorithm; RSA;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computing, Communications and Networking Technologies (ICCCNT),2013 Fourth International Conference on
Conference_Location :
Tiruchengode
Print_ISBN :
978-1-4799-3925-1
Type :
conf
DOI :
10.1109/ICCCNT.2013.6726464
Filename :
6726464
Link To Document :
بازگشت