NPN transistor improvement by cumulative resist processing

A method for improving the performance of a single polysilicon NPN transistor by using cumulative/dual photoresist processing is presented. The photoresist from the polysilicon emitter layer patterning is preserved and over-coated in the subsequent extrinsic base implant masking layer. The n-type emitter polysilicon is thus protected from counter-doping by the p-type extrinsic base implantation in a self-aligned manner. Electrical consequences of applying this process, which include improved current gain and cutoff frequency, are reported.