Dual-rail multiple-valued current-mode VLSI with biasing current sources

Author

Ike, Tsukasa ; Hanyu, Takahiro ; Kameyama, Michitaka

Author_Institution

Dept. of Comput. & Math. Sci., Tohoku Univ., Sendai, Japan

fYear

2001

fDate

2001

Firstpage

21

Lastpage

26

Abstract

A new current mirror with a biasing current source is proposed for high-performance arithmetic VLSI systems. The delay for the current mirror is inversely proportional to the input current. The use of a biasing current source makes the input current of the current mirror increased, which results in smaller switching delay. As a typical example of the proposed dual-rail multiple-valued current mode (MVCM) circuit, a radix-2 signed-digit full adder is designed by using a 0.35-μm CMOS technology. Its performance is superior to that of corresponding MVCM circuits without biasing current sources

Keywords

CMOS logic circuits; VLSI; adders; current mirrors; current-mode circuits; multivalued logic circuits; CMOS technology; biasing current sources; current mirror; dual-rail multiple-valued current-mode VLSI; high-performance arithmetic VLSI systems; radix-2 signed-digit full adder; switching delay; Adders; CMOS technology; Circuits; Delay; Detectors; Low voltage; Mirrors; Power dissipation; Threshold voltage; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Multiple-Valued Logic, 2001. Proceedings. 31st IEEE International Symposium on

Conference_Location

Warsaw

ISSN

0195-623X

Print_ISBN

0-7695-1083-3

Type

conf

DOI

10.1109/ISMVL.2001.924550

Filename

924550