Efficient controller architectures for DSP compilers

The current generation of digital-signal-processing (DSP) chips is able to handle regular arithmetic operations in an efficient way but has problems with decision-making irregular algorithms. The reason is that decisions are taken by branching in the microcode, and the efficiency of these branches is limited by pipelines in the controller. The author looks for controller architectures that allow much more efficient implementations of decision-making algorithms. These architectures will be used as target architectures in a silicon compilation environment. Therefore they have to be flexible and parametrizable such that they can be adapted to the requirements of a particular application