• DocumentCode
    3120499
  • Title

    Tunnelling diode technology

  • Author

    Prost, W. ; Auer, U. ; Tegude, F.J. ; Pacha, C. ; Goser, K.F. ; Dusc, R. ; Eberl, K. ; Hmidt, O. G Sc

  • Author_Institution
    Dept. of Solid-State Electron., Duisburg Univ., Germany
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    49
  • Lastpage
    58
  • Abstract
    The technology of quantum tunnelling devices, namely III/V double barrier Resonant Tunnelling Diodes (RTD) and Si/SiGe Interband Tunnelling Diodes (ITD), is studied for logic circuit applications. The homogeneity and reproducibility of MBE grown InP-based RTD devices with mesa technology is presented. Si/SiGe ITD have been grown by MBE on high resistivity (n-) Silicon substrates. A novel self-aligned diode is processed using optical lithography and dopant-selective wet chemical etching. Comparing RTD and ITD data the differences are due to the vertical spacing of the doped layers within the device. A nanoelectronic circuit architecture based on an improved MOBILE threshold logic gate is used. SPICE simulations are carried-out in order to evaluate tolerable clock and supply voltage fluctuations in comparison to device fluctuations
  • Keywords
    III-V semiconductors; SPICE; etching; logic circuits; logic design; molecular beam epitaxial growth; photolithography; resonant tunnelling diodes; threshold logic; III/V double barrier resonant tunnelling diodes; MBE grown InP-based RTD devices; SPICE simulations; Si/SiGe interband tunnelling diodes; device fluctuations; dopant-selective wet chemical etching; homogeneity; logic circuit; mesa technology; nanoelectronic circuit architecture; optical lithography; quantum tunnelling devices; self-aligned diode; threshold logic gate; tolerable clock; vertical spacing; Chemical technology; Conductivity; Diodes; Fluctuations; Germanium silicon alloys; Lithography; Logic circuits; Reproducibility of results; Resonant tunneling devices; Silicon germanium;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Multiple-Valued Logic, 2001. Proceedings. 31st IEEE International Symposium on
  • Conference_Location
    Warsaw
  • ISSN
    0195-623X
  • Print_ISBN
    0-7695-1083-3
  • Type

    conf

  • DOI
    10.1109/ISMVL.2001.924554
  • Filename
    924554