Title :
Optimizing pattern fill for planarity and parasitic capacitance
Author :
Nelson, M. ; Williams, B. ; Belisle, C. ; Aytes, S. ; Beasterfield, D. ; Liu, J. ; Donaldson, S. ; Prasad, J.
Author_Institution :
AMI Semicond., Pocatello, ID, USA
Abstract :
In integrated circuit manufacturing with multi-level interconnect, it is important to have a planar surface preceding the next layer to avoid topography-induced patterning failure. In this paper, we describe a method for optimizing the use of pattern fill for planarity of CMP processing against the parasitic capacitive effects generated by such fill. Results applying this methodology on a seven metal product set are used to demonstrate its effectiveness.
Keywords :
capacitance; chemical mechanical polishing; circuit optimisation; integrated circuit interconnections; integrated circuit manufacture; integrated circuit metallisation; CMP processing; integrated circuit manufacturing; metal product set; multilevel interconnect; optimizing pattern fill; parasitic capacitance; parasitic capacitive effects; planarity capacitance; topography; Active circuits; Coupling circuits; Dielectric measurements; Failure analysis; Optical feedback; Parasitic capacitance; Pattern analysis; Performance analysis; Surfaces; Thickness measurement;
Conference_Titel :
Advanced Semiconductor Manufacturing, 2004. ASMC '04. IEEE Conference and Workshop
Print_ISBN :
0-7803-8312-5
DOI :
10.1109/ASMC.2004.1309547
