Title :
Method for calculating high-resolution wafer parameter profiles
Author :
Abercrombie, David ; Whitefield, Bruce
Author_Institution :
LSI Logic, Gresham, OR, USA
Abstract :
This paper describes a method to use parametric or yield data from many different products and die sizes for generating highly detailed wafer profiles. These profiles have an improved signal to noise ratio and spatial resolution compared to traditional wafer maps. This technique takes advantage of multiple die sizes and their variation in placement on the wafer to increase the information available about the wafer patterns. Several potential applications of these profiles were discussed.
Keywords :
data analysis; integrated circuit yield; semiconductor process modelling; die sizes; high resolution wafer parameter profiles; multiple die sizes; parametric data; signal-to-noise ratio; spatial resolution; wafer maps; wafer patterns; yield data; Area measurement; Data engineering; Data visualization; Diversity reception; Inspection; Large scale integration; Pattern analysis; Signal to noise ratio; Spatial resolution; Thickness measurement;
Conference_Titel :
Advanced Semiconductor Manufacturing, 2004. ASMC '04. IEEE Conference and Workshop
Print_ISBN :
0-7803-8312-5
DOI :
10.1109/ASMC.2004.1309548
