Title :
VHDL implementation of UART with BIST capability
Author :
Patel, Naresh ; Patel, Naresh
Author_Institution :
Sagar Inst. of Res. & Tech., Bhopal, India
Abstract :
Manufacturing processes are extremely complex, inducing manufacturers to consider testability as a requirement to assure the reliability and the functionality of each of their designed circuits. One of the most popular test techniques is called Built-In-Self-Test (BIST). A Universal Asynchronous Receive/Transmit (UART) with BIST capability has the objectives of testing the UART on chip itself and no external devices are required to perform the test. This paper focuses on the VHDL implementation of UART with embedded BIST capability using FPGA technology. The paper presents the architecture of UART with BILBO which tests the UART for its correctability. The whole design is synthesized and verified using Xilinx ISE Simulator and Modelsim Simulator.
Keywords :
built-in self test; computer interfaces; digital simulation; field programmable gate arrays; hardware description languages; integrated circuit design; BILBO; BIST capability; FPGA technology; Modelsim simulator; UART; VHDL implementation; Xilinx ISE simulator; built-in-self-test; designed circuits; manufacturing processes; universal asynchronous receive-transmit; Built-in self-test; Clocks; Receivers; Shift registers; Transmitters; BILBO; Built In Self Test; Universal Asynchronous Receiver Transmitter; VHDL implementation;
Conference_Titel :
Computing, Communications and Networking Technologies (ICCCNT),2013 Fourth International Conference on
Conference_Location :
Tiruchengode
Print_ISBN :
978-1-4799-3925-1
DOI :
10.1109/ICCCNT.2013.6726476
