Multiple-valued mask-programmable logic array using one-transistor universal-literal circuits

Author

Hanyu, Takahiro ; Kameyama, Michitaka ; Shimabukuro, Katsuhiko ; Zukeran, Chotei

Author_Institution

Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan

fYear

2001

fDate

2001

Firstpage

167

Lastpage

172

Abstract

This paper presents a compact multiple-valued mask-programmable logic array (MPLA) based on a MIN/TSUM (MINimum/Truncated-SUM) two-level synthesis. A universal literal in the MIN plane is decomposed into a threshold literal and a logic-value conversion (LVC) that is shared in the same column of the MIN plane. Since a threshold literal can be designed by using a single floating-gate MOS transistor, a compact MIN plane can be implemented in the proposed MPLA. Any arbitrary universal-literal circuits can be realized by programming the threshold voltage of the corresponding floating-gate MOS transistor and selecting an appropriate LVC as an input variable. The performance of the proposed MPLA is evaluated under a 0.8 μm CMOS design. It is demonstrated that its performance is superior to that of conventional PLA´s

Keywords

CMOS logic circuits; multivalued logic circuits; programmable logic arrays; CMOS design; MIN plane; MIN/TSUM; floating-gate MOS transistor; logic-value conversion; multiple-valued mask-programmable logic array; one-transistor universal-literal circuits; performance; threshold literal; two-level synthesis; CMOS logic circuits; CMOS process; Hardware; Input variables; Logic arrays; Logic circuits; Logic devices; MOSFETs; Programmable logic arrays; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Multiple-Valued Logic, 2001. Proceedings. 31st IEEE International Symposium on

Conference_Location

Warsaw

ISSN

0195-623X

Print_ISBN

0-7695-1083-3

Type

conf

DOI

10.1109/ISMVL.2001.924568

Filename

924568