DocumentCode
3121350
Title
Analysis of wafer process duration for ab initio calculation of capacity, throughput and bottleneck equipments in a wafer fab
Author
Etzel, H. ; Staudt, P. ; Oertel, J. ; Dudde, R.
Author_Institution
Flensburg Univ. of Appl. Sci., Germany
fYear
2004
fDate
4-6 May 2004
Firstpage
330
Lastpage
333
Abstract
The production flow in a mid sized state of the art wafer fab has been used for the statistical analysis. In this paper, we report on an evaluation of wafer booking times for an analysis of equipment utilization and wafer fab capacity which turned out to be an easy tool to provide actual information on process steps and overall fab utilization and capacity.
Keywords
ab initio calculations; cleaning; electronics industry; flow shop scheduling; integrated circuit manufacture; production engineering computing; semiconductor technology; ab initio calculation; bottleneck equipments; equipment utilization; fab capacity; porcess steps; production flow; wafer process duration; Conductors; Data mining; Flow production systems; Information analysis; MOSFETs; Manufacturing automation; Production control; Silicon; Software packages; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing, 2004. ASMC '04. IEEE Conference and Workshop
Print_ISBN
0-7803-8312-5
Type
conf
DOI
10.1109/ASMC.2004.1309591
Filename
1309591
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