"Extreme edge engineering" - 2 mm edge exclusion challenges and cost-effective solutions for yield enhancement in high volume manufacturing for 200 and 300 mm wafer fabs

Author

Tran, Thy ; Roberts, William ; Tiffany, Jason ; Jekauc, Lgor ; Clements, Nicholas ; Jowett, Paul ; Ferguson, Reuben ; Mattson, Dan ; Demmert, Cort ; Richmond, Mark ; Wiendl, Christian ; Bruno, Michael ; Brock, Aaron ; Taylor, Thomas

Author_Institution

Infineon Technol., Richmond, VA, USA

fYear

2004

fDate

4-6 May 2004

Firstpage

453

Lastpage

460

Abstract

Significant financial benefits are realized by reducing the wafer edge exclusion to gain additional productive chips as well as enhance the yield of the former edge-most region of the wafer. Challenges are discussed and cost-effective solutions provided for major unit process and integration issues such as plasma-etch induced blocked/distorted pattern, image displacement, interlayer misalignment, lithography edge coating and patterning, pattern-density-dependent CMP and Etch non-uniformity, scribe readability, and shared-driver shorts.

Keywords

chemical mechanical polishing; etching; integrated circuit yield; lithography; wafer bonding; chemical mechanical polishing; cost effective solutions; etch nonuniformity; extreme edge engineering; former edge most region; image displacement; interlayer misalignment; lithography edge coating; lithography edge patterning; pattern density dependent CMP; plasma etch induced blocked pattern; plasma etch induced distorted pattern; scribe readability; shared driver shorts; wafer edge exclusion; wafer fabs; yield enhancement; Assembly; Coatings; Etching; Hardware; Manufacturing; Nonlinear distortion; Plasma applications; Semiconductor device modeling; Testing; Vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing, 2004. ASMC '04. IEEE Conference and Workshop

Print_ISBN

0-7803-8312-5

Type

conf

DOI

10.1109/ASMC.2004.1309614

Filename

1309614