Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations

Author

Venugopalan, S. ; Chauhan, Y.S. ; Lu, D.D. ; Karim, M.A. ; Niknejad, Ali M. ; Hu, Chenming

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, Berkeley, CA, USA

fYear

2011

fDate

7-9 Nov. 2011

Firstpage

1

Lastpage

4

Abstract

In a vertical cylindrical gate transistor, we identify doping gradation along channel and structural difference in electrode regions as major reasons for highly asymmetric drain current characteristics. These effects have been captured in a physical manner in a SPICE model. Calibration results of such a model to silicon device data from a vertical cylindrical gate technology that exhibits asymmetric I-V characteristics is presented for the first time.

Keywords

SPICE; circuit simulation; electrodes; field effect transistors; semiconductor doping; 3D cylindrical gate; SPICE model; asymmetric I-V characteristic; circuit simulation; doping gradation; drain current characteristic; electrode region; extrinsic asymmetry; gate-all-around FET; intrinsic asymmetry; silicon device data; vertical cylindrical gate transistor; Doping; FETs; Integrated circuit modeling; Junctions; Logic gates; Semiconductor process modeling; Asymmetric Transistor Modeling; BSIM SPICE Compact Model; Vertical Cylindrical/Surround Gate Transistor;

fLanguage

English

Publisher

ieee

Conference_Titel

Non-Volatile Memory Technology Symposium (NVMTS), 2011 11th Annual

Conference_Location

Shanghai

Print_ISBN

978-1-4577-1428-3

Type

conf

DOI

10.1109/NVMTS.2011.6137100

Filename

6137100