Title :
Integrated pin electronics for VLSI functional testers
Author :
Gasbarro, James A. ; Horowitz, Mark A.
Author_Institution :
Xerox Palo Alto Res. Center, CA, USA
Abstract :
A novel method is presented for building high-performance pin electronics circuitry using conventional CMOS technology. To demonstrate the feasibility of these circuit techniques, a prototype processing-element chip consisting of four I/O channels was designed in a 2-μm double-metal CMOS technology. It contains 13 K transistors in a die size of 3.9 mm×5.3 mm. Running at 33 Mvectors/s, the chip dissipates 125 mW with a 5-V supply. The authors feel that it is possible to build practical integrated pin electronics for functional VLSI testers with a technology only as good as that of the design under test
Keywords :
CMOS integrated circuits; VLSI; automatic test equipment; integrated circuit testing; 125 mW; 2 micron; 5 V; 5.3 mm; VLSI functional testers; VLSI testers; conventional CMOS technology; die size; double-metal CMOS technology; high-performance pin electronics circuitry; prototype processing-element chip; CMOS technology; Calibration; Circuit testing; Delay effects; Electronic equipment testing; Integrated circuit technology; Pins; Pulse generation; Timing; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20878
