Test power minimization of VLSI circuits: A survey

Modern IC design and manufacturing techniques are growing such that the transistor count on a single chip escalates exponentially with complex Embedded and DSP cores in it. Hence, testing of such complex ICs are extremely challenging. It is a well-known fact that test power is several times higher than functional power. Today´s Ultra-Low Power devices in deep sub-micron technologies used for embedded applications in bio-medical electronics, wireless sensor networks and sophisticated battery operated portable electronic products such as laptops, cell phones, audio-video based multimedia products makes power management a critical parameter for test engineers. This survey paper first gives an overview of the need and importance of reducing test power of VLSI circuits. Next, a detailed survey of, recent approaches towards low power testing of high density VLSI circuits are presented. A comparison of, newly developed test solutions with respect to key parameters of low power testing like, test power, test energy, node switching activity and so on is presented for choosing a best possible solution. Finally, an insight towards benchmark circuits to be used for testing and EDA tools available for DFT is discussed. Good periodical survey in any research area is essential for better understanding of its basics and it also indicates the trends and scope for future research in the chosen area.