Complementary LDMOSFET in 0.35μm BiCMOS technology-characterization and modeling

In this paper, an nLDMOS and a pLDMOS are developed by slight modifications of the base process steps of 0.35μm BiCMOS technology. Extra two masks are used for the formation of the body region and the drift region with slightly added thermal budget and without resorting to high-tilt implants. The specific ON-resistance (R_ON,SP) and the OFF-state breakdown voltage(BV) are 1.5 mΩcm² and 60V, for the nLDMOS and 3.0 mΩcm² and 160V, for the pLDMOS. So, the devices can typically be operated around 42V supply voltage, which is suitable for the new automotive applications. A simple subcircuit model is built using a two module approach, one for the intrinsic MOS area and the other for the drift region. The PSpice model parameters of the intrinsic MOS part are extracted using a system that links the ICCAP extraction tool with the results of the ISETCAD tools. The simulation results using the PSpice model are compared to the results provided by ISE-TCAD tools, and the accuracy at room temperature is less than 5% for the whole voltage domain. An interface circuit, to convert 0/3.3 V to 0/42 V, suitable for automotive applications is proposed.