Bottom-up testing methodology for VLSI

Author

Teixeira, J.P. ; Almeida, C.F.B. ; Gracio, J.A. ; Bicudo, P.A. ; Oliveira, A.L. ; Rua, N.

Author_Institution

INESC, IST, Lisbon, Portugal

fYear

1988

fDate

16-19 May 1988

Abstract

A testing methodology for digital VLSI circuits is proposed that is based on the definition of a realistic fault list, which depends on the technology, the manufacturing process, and the IC layout. Automatic fault listing is carried out by a hierarchical layout-to-fault extractor, LIFE. Fault-list compression is performed according to user-defined fault listing objectives. Test-pattern validation is made by an accurate switch-level fault simulator with timing information capabilities, SWIFT. The methodology and the correspondent software tools can be used in the IC design and production testing environments. At present, the two software tools are to be included in the ICD tool box, in a workstation-based IC design environment

Keywords

VLSI; automatic test equipment; digital integrated circuits; integrated circuit testing; IC design; IC layout; LIFE; SWIFT; automatic fault listing; bottom up test methodology; digital VLSI circuits; fault list compression; hierarchical layout-to-fault extractor; manufacturing process; production testing environments; realistic fault list; software tools; switch-level fault simulator; test pattern validation; timing information capabilities; user-defined fault listing objectives; workstation-based IC design environment; Circuit faults; Circuit testing; Data mining; Digital integrated circuits; Integrated circuit layout; Integrated circuit testing; Manufacturing processes; Software tools; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/CICC.1988.20882

Filename

20882