Design and FPGA implementation of binary squarer using Vedic mathematics

Author

Sriraman, L. ; Kumar, K. Sathish ; Prabakar, T.N.

Author_Institution

Dept. of Electron. & Commun. Eng., Oxford Eng. Coll., Trichy, India

fYear

2013

fDate

4-6 July 2013

Firstpage

1

Lastpage

5

Abstract

In this paper, a squarer based on Vedic mathematics is proposed. Vedic mathematics is one of the ancient Indian mathematics which contains sixteen sutras. These sutras can be used to solve problems in any branch of Mathematics in a faster way. The proposed squarer is based on sutra called Ekadhikena Purvena. It means that “one more than the previous”. This sutra is used for finding the square of decimal numbers ending with `5´. In this paper this sutra is generalized and used for squaring of binary numbers. The proposed squarer is compared with duplex squarer for 8, 16 and 32-bit cases in Cyclone III FPGA EP3C16F484C6. The proposed squarer saves area by almost 50% and reduces delay by 50% when compared with duplex squarer in 32-bit case.

Keywords

digital arithmetic; field programmable gate arrays; logic design; Cyclone III FPGA EP3C16F484C6; Ekadhikena Purvena; FPGA implementation; Vedic mathematics; ancient Indian mathematics; binary numbers; binary squarer; decimal numbers; duplex squarer; sixteen sutras; word length 16 bit; word length 32 bit; word length 8 bit; Arrays; Delays; Digital signal processing; Field programmable gate arrays; Hardware; Mathematics; Duplex squarer; Ekadhikena Purvena; FPGA; Squarer; Vedic Mathematics;

fLanguage

English

Publisher

ieee

Conference_Titel

Computing, Communications and Networking Technologies (ICCCNT),2013 Fourth International Conference on

Conference_Location

Tiruchengode

Print_ISBN

978-1-4799-3925-1

Type

conf

DOI

10.1109/ICCCNT.2013.6726607

Filename

6726607