Impact of process scaling on the efficacy of leakage reduction schemes

Author

Tsai, Yuh-Fang ; Duarte, David ; Vijaykrishnan, N. ; Irwin, Mary Jane

Author_Institution

Pennsylvania State Univ., University Park, PA, USA

fYear

2004

fDate

2004

Firstpage

3

Lastpage

11

Abstract

The effects of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) are evaluated by determining their limits and benefits, in terms of the potential leakage reduction, performance penalty and area and power overhead in 0.25μm, 0.18μm, 0.07μm and 0.065μm technologies. HSPICE simulation results and estimations with various function units and memory structures are presented to support a comprehensive analysis.

Keywords

CMOS integrated circuits; SPICE; integrated circuit modelling; leakage currents; low-power electronics; HSPICE simulation; area overhead; body bias control; datapath logic; input vector control; leakage reduction scheme efficacy; low power; multiple threshold voltage CMOS; performance penalty; potential leakage reduction; power overhead; power supply gating; process scaling; process variations; run-time leakage reduction; technology scaling; Analytical models; Circuits; Dielectric materials; Dynamic voltage scaling; Power supplies; Power system dynamics; Runtime; Semiconductor device measurement; Stacking; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on

Print_ISBN

0-7803-8528-4

Type

conf

DOI

10.1109/ICICDT.2004.1309890

Filename

1309890