A 100 MegaFlop double precision IEEE multiplier block for advanced bipolar VLSI

Details of its construction and use are presented for the MPY54APM multiplier megacell, an ultrahigh-performance double-precision IEEE-754 floating-point multiplier, capable of better than 100 MFLOPS (million floating-point operation per second) throughput. The MPY54APM was designed to minimize delay. To this end it performs 54-bit multiplication on two two´s-complement numbers with a throughput delay of less than 9 ns per product. The typical application is a three-stage pipelined architecture. Two of these megacells are cascaded to form two of the pipeline stages, each with a 9-ns delay. The last stage is constructed of standard cells to perform final carry-lookahead addition normalization, rounding, and exception limiting. The adjunct operations on the exponent fields for floating-point multiplication occur concurrently with the mantissa operations