A 0.18 μm 4 Mbit toggling MRAM

Author

Durlam, M. ; Addie, D. ; Akerman, J. ; Butcher, B. ; Brown, P. ; Chan, J. ; DeHerrera, M. ; Engel, B.N. ; Feil, B. ; Grynkewich, G. ; Janesky, J. ; Johnson, M. ; Kyler, K. ; Molla, J. ; Martin, J. ; Nagel, K. ; Nahas, J. ; Ren, J. ; Rizzo, N.D. ; Rodrigue

Author_Institution

Semicond. Products Sector, Motorola Inc., Chandler, AZ, USA

fYear

2004

fDate

2004

Firstpage

27

Lastpage

30

Abstract

A 4 Mbit Magnetoresistive Random Access Memory (MRAM) with a new magnetic switching mode is described. The memory cell is based on a 1-Transistor 1-Magnetic Tunnel Junction (1T1MTJ) bit cell. The 4 Mbit MRAM circuit was designed in a five level metal, 0.18 μm CMOS process with a bit cell size of 1.55 μm². A new cell architecture, bit structure, and switching mode improve the operational performance of the MRAM as compared to conventional MRAM. The 4 Mbit circuit is the largest MRAM memory demonstration to date.

Keywords

CMOS memory circuits; magnetic switching; magnetic tunnelling; magnetoelectronics; magnetoresistive devices; random-access storage; spin polarised transport; 4 Mbit; bit magnetic reversal energy barrier; bit structure; cell architecture; five level metal CMOS process; magnetic switching mode; magnetic tunnel junction; magnetoresistive random access memory; nonvolatile memory; operational performance; spin polarized electrons; CMOS process; Delay; Electric resistance; Electrodes; Electrons; Energy barrier; Magnetic separation; Magnetic switching; Magnetic tunneling; Polarization;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on

Print_ISBN

0-7803-8528-4

Type

conf

DOI

10.1109/ICICDT.2004.1309899

Filename

1309899