Title :
An embedded silicon nanocrystal nonvolatile memory for the 90nm technology node operating at 6V
Author :
Muralidhar, R. ; Steimle, R.F. ; Sadd, M. ; Rao, R. ; Swift, C.T. ; Prinz, E.J. ; Yater, J. ; Grieve, L. ; Harber, K. ; Hradsky, B. ; Straub, S. ; Acred, B. ; Paulson, W. ; Chen, W. ; Parker, L. ; Anderson, S.G.H. ; Rossow, M. ; Merchant, T. ; Paransky, M
Author_Institution :
Freescale Semicond., Technol. Solutions Organ., Austin, TX, USA
Abstract :
This paper reports on the first functional 6V, 4Mb silicon nanocrystal based nonvolatile memory array using conventional 90nm and 0.25μm process technologies. The silicon nanocrystal based NOR Flash can be programmed and erased using conventional techniques in floating gate memories. Key aspects of this technology are the ability to form nanocrystals of the right size and density, the ability to protect them from subsequent processing effects and the ability to remove them from undesired areas. The use of isolated silicon nanocrystals for charge storage provides the opportunity to reduce the program and erase voltages due to tunnel oxide scaling and also has potential for two bits/cell operation. Optimization of tunnel and control oxides is critical to obtain high program/erase cycling endurance. Due to the area savings from memory module peripheral voltage scaling and the reduction in mask count over conventional floating gate technology, silicon nanocrystal non-volatile memory technology can substantially reduce the cost of embedded flash at the 90nm technology node and beyond.
Keywords :
CMOS memory circuits; elemental semiconductors; flash memories; nanoelectronics; silicon; 4 Mbit; 6 V; 90 nm; CMOS flow; NOR flash; Si; area savings; bit cell characteristics; charge storage; embedded silicon nanocrystal; floating gate memories; isolated silicon nanocrystals; mask count; nonvolatile memory; peripheral voltage scaling; CMOS logic circuits; CMOS process; CMOS technology; Human computer interaction; Nanocrystals; Nonvolatile memory; SONOS devices; Silicon; Tunneling; Voltage;
Conference_Titel :
Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on
Print_ISBN :
0-7803-8528-4
DOI :
10.1109/ICICDT.2004.1309900